(1) Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a bipolar transistor having a thin intrinsic base with a low base resistance and a method for fabricating the same.
(2) Description of the Related Art
It is known that, in the bipolar transistor, the thinner the base the higher the cut-off frequency will be with this being a yardstick for a higher speed performance. It is also known that to lower the resistance of the base leading portions and to scale down the transistor are effective for achieving a higher speed in the transistor.
FIG. 1 shows in diagrammatic sectional view an earlier proposed semiconductor device disclosed in Japanese Patent Application Kokai Publication No. Hei 4-330730 (in which the inventor is one of the co-inventors in the present application). In the case of the disclosed device, the reduction in the thickness of the base layer is realized by forming a base and an emitter using a low temperature epitaxial growth technique without using a diffusion process therein.
In the proposed device, as shown in FIG. 1, an n.sup.+ -type buried layer 2 in which a high concentration Arsenic (As) is introduced is selectively formed within a surface region of a p-type silicon substrate 1 whose resistivity is 10.about.15 .OMEGA.-cm. On the buried layer 2, there is formed an n-type epitaxial layer 3 having a thickness of 1.0 82 m in which an n-type impurity in a concentration in the order of 5.times.10.sup.15 cm.sup.-3 is introduced. The n-type epitaxial layer 3 is separated, by a known selective oxidation process, into a plurality of island regions by a selective oxide film 4 which reaches the silicon substrate 1. For simplification of the drawings, FIG. 1 shows only one island region corresponding to one n-type buried region 2. This island region is separated into two portions by a selective oxide film 4a which reaches the buried region 2. The portion at the left hand functions as a collector region. The portion at the right hand is subjected to phosphorous diffusion to make it an n.sup.+ -type diffusion layer 8 which serves as a region from which the collector is led out. This is how the semiconductor substrate 100 is formed.
The semiconductor substrate 100 is covered with a silicon nitride film 5a. In this film, there are formed an opening 101 which exposes a part of the collector region (epitaxial layer 3) for forming the base and another opening 102 which exposes an upper surface of the n.sup.+ -type diffusion layer 8 for leading out the collector. Preferably, a thin silicon oxide film is provided under the silicon nitride film 5a.
On the silicon nitride film 5a, there are selectively formed a p-type polycrystalline silicon layer 8 and an n-type polycrystalline silicon layer 7.
The polycrystalline silicon layer 6 horizontally extends into the opening 101 from the edge thereof. A p-type polycrystalline silicon layer 13 is formed between the undersurface of the horizontally extended portion of the polycrystalline silicon layer 6 and the epitaxial layer 3 which is the collector region. On the other hand, on the exposed part of the epitaxial layer 3, there is formed a p-type base region 14c by an epitaxial growth process as described in the Japanese Patent Application Kokai Publication referred to above. This base region 14c and the polycrystalline silicon layer 13 are in contact with each other.
An n-type polycrystalline silicon layer 7 formed in the other opening 102 is in contact with the n.sup.+ -type diffusion layer 8 which is the region for leading out the collector.
The upper and side surfaces of the polycrystalline silicon layer 8 are covered with the silicon oxide film 11a which has an emitter opening on an emitter forming region. In this emitter opening, the side surfaces of the polycrystalline silicon layer 13 and the silicon oxide film 11a are covered with a silicon oxide film 15a.
In the exposed part of the base region 14c, there is formed an n-type single-crystal silicon film 16 which constitutes the emitter region.
On each of the polycrystalline silicon layers 6, 7 and the single-crystal silicon layer 16, there is formed a metal electrode 17 of an aluminum (Al) type material.
In the semiconductor device proposed in the Japanese Patent Application Kokai Publication referred to above, the Boron concentration of the base region portion immediately beneath the emitter region (single-crystal silicon layer 16) which is the intrinsic base and the Boron concentration of the base link region constituted by the non-intrinsic portion of the base region 14c and the polycrystalline silicon layer 13 are substantially the same with each other. Also, the thickness of the base link region right beneath the silicon oxide film 15a is substantially the same as the thickness of the intrinsic base region, so that sheet resistance at the base link region becomes considerably high. As a result, the base resistance increases and a high speed operation of the transistor is hindered. That is, with the transistor having the above described configuration, it is difficult to achieve both the reduction in the thickness of the Intrinsic base and the reduction in the base resistance at the same time.